Engr 325 homework 5 key - Study guides, Class notes & Summaries

(5) Assume that the logic blocks needed to implement a processor’s datapath have the latencies shown in the table below. These problems refer to the datapath element Shift-Left-2. (P&H 4.4, §4.3) Block Latency (ps) I-Mem 200 Add 70 Mux 20 ALU 90 Regs 90 D-Mem 250 Sign-Extend 15 Shift-Left-2 10 a. Which kinds of instructions require this resource? b. For which kinds of instructions (if any) is this resource on the critical path? SOLUTION:

ENGR 325 HOMEWORK #7 KEY FALL 2015 1. (5) In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. Assume each word is a 32-bit integer. (P&H 5.1, §5.1) for (I=0; I<8; I++) for (J=0; J<8000; J++) A[I][J]=B[I][0]+A[J][I]; a. How many 32-bit integers can be stored in a 16-byte cache block? b. References to which variables exhibit temporal locality? c. References to...

ENGR 325 HOMEWORK 7 KEY. 1. (5) In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. Assume each word is a 32-bit integer. (P&H 5.1, §5.1) for (I=0; I<8; I++) for (J=0; J<8000; J++) A[I][J]=B[I][0]+A[J][I]; a. How many 32-bit integers can be stored in a 16-byte cache block? b. References to which variables exhibit temporal locality? c. References to which variab...

ENGR 325 HOMEWORK #7 KEY FALL 2015