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2024 RISC-V CSC 225 MC Exam Questions & Answers

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2024 RISC-V CSC 225 MC Exam Questions & Answers Which one of the following is true about Control Instructions? a) They include lw, lb, sw, and la b) They modify the program counter c) They are unconditional d) They modify the instructions stored in memory e) They modify the data stored in...

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  • November 15, 2024
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  • 2024 RISC-V CSC 225 MC
  • 2024 RISC-V CSC 225 MC
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2024 RISC-V CSC 225 MC Exam
Questions & Answers

Which one of the following is true about Control Instructions?

a) They include lw, lb, sw, and la

b) They modify the program counter

c) They are unconditional

d) They modify the instructions stored in memory

e) They modify the data stored in memory

f) None of the above - ANSWERSb



What is the main difference between Harvard and Von Neumann architectures?

a) Arithmetic operations can access memory

b) There are more registers

c) There are separate memories for instructions and data

d) All of the above

e) None of the above - ANSWERSc



Which statement is not true of an RV64IMF RISC-V processor?

a) It supports multiply instructions

b) the registers are 64 bits each

c) there are 64 General Purpose registers

d) it supports floating point instructions

e) all statements are true - ANSWERSc



On a Von Neumann Machine, a value that exists in computer memory can represent:

a) data

, b) an instruction

c) an invalid instruction

d) either a or b

e) all of the above - ANSWERSe



An assembler directive is:

a) implemented using a different CPU instruction

b) ignored during the assembly process

c) an instruction to the assembler during the assembly process

d) translated into a binary encoded CPU instruction

e) none of the above - ANSWERSc



What is the maximum size of the immediate value in the addi instruction?

+/- 2KB

the full range of memory

+/- 4K

whatever is in the Rs

none of the above - ANSWERSa



which instruction would you use to clear only bit 4 of a register?

add

and

or

li

none of the above - ANSWERSb



which item can we not determine knowing that the processor is an RV64IMF RISC-V processor?

supported instructions

address space

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