WGU C952 PRACTICE EXAM
control hazard (branch hazard) - Answer-When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected.
Br...
control hazard (branch hazard) - Answer-When the proper instruction cannot execute in
the proper pipeline clock cycle because the instruction that was fetched is not the one
that is needed; that is, the flow of instruction addresses is not what the pipeline
expected.
Branch prediction - Answer-A method of resolving a branch hazard that assumes a
given outcome for the branch and proceeds from that assumption rather than waiting to
ascertain the actual outcome.
five-stage pipeline - Answer-five instructions will be in execution during any single clock
cycle
1. IF - instruction fetch
2. ID - instruction decode and register file read
3. EX - execution or address calculation
4. MEM - data memory access
5. WB - write back
Instruction Fetch (IF) - Answer-Move instruction from memory to the control unit
Instruction decode (ID) - Answer-Pull apart the instruction, set up the operation in the
ALU, and compute the source and destination operand addresses
Execute (EX) - Answer-ALU is used to perform the instruction's operation or to compute
an address, or an adder is used for branches; both are depicted using an ALU symbol.
Data memory access (MEM) - Answer-the data memory (DM) may be read (for a load
instruction) or written (for a store instruction). For load, the right half is shaded,
indicating read. (For store, the left half would be shaded).
Write back (WB) - Answer-the register file (Reg) may be written by certain instructions
(like R-type instructions). The left half is shaded to indicate write (vs. read). Although
two Reg icons appear in the stylized depictions, only one register file exists.
Branch prediction buffer - Answer-Also called branch history table. A small memory that
is indexed by the lower portion of the address of the branch instruction and that contains
one or more bits indicating whether the branch was recently taken or not.
, Dynamic branch prediction - Answer-prediction of branches at runtime using runtime
information
Branch target buffer - Answer-A structure that caches the destination PC or destination
instruction for a branch. It is usually organized as a cache with tags, making it more
costly than a simple prediction buffer.
Correlating predictor - Answer-A branch predictor that combines local behavior of a
particular branch and global information about the behavior of some recent number of
executed branches.
Tournament branch predictor - Answer-A branch predictor with multiple predictions for
each branch and a selection mechanism that chooses which predictor to enable for a
given branch.
Microarchitecture - Answer-The organization of the processor, including the major
functional units, their interconnection, and control.
Architectural registers - Answer-The instruction set of visible registers of a processor;
for example, in MIPS, these are the 32 integer and 16 floating point registers
Three Cs model - Answer-A cache model in which all cache misses are classified into
one of three categories: compulsory misses, capacity misses, and conflict misses.
compulsory miss (cold-start miss) - Answer-a cache miss caused by the first access to a
block that has never been in the cache
Both large block sizes and prefetching may reduce compulsory misses
capacity miss - Answer-A cache miss that occurs because the cache, even with full
associativity, cannot contain all the blocks needed to satisfy the request.
Increase cache size may decrease capacity misses and increase access time
conflict miss (collision miss) - Answer-A cache miss that occurs in a set-associative or
direct-mapped cache when multiple blocks compete for the same set and that are
eliminated in a fully associative cache of the same size
Increases associativity may decrease miss rate and increase access time.
Finite-state machine - Answer-A sequential logic function consisting of a set of inputs
and outputs, a next-state function that maps the current state and the inputs to a new
state, and an output function that maps the current state and possibly the inputs to a set
of asserted outputs.
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