C952 CERTIFICATION EXAM QUESTIONS WITH CORRECT ANSWERS
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Course
C952
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C952
C952 CERTIFICATION EXAM QUESTIONS WITH CORRECT ANSWERS
What is the address of the next instruction that should execute after the branch if the register X1 is equal to 0?
28 SUB X12, X4, X8
32 CBZ X1, X5, 5
36 AND X13, X4, X7
40 ORR X14, X4, X8
44 ADD X14, X6, X4
48 SUB X15, X8, X9 ...
How can the CPU performance of a program be improved? - Answer-By reducing the
number of clock cycles
A program runs alone on a CPU. The CPU clock rate is 3e9 cycles per second, i.e., 3
GHz. It takes the CPU 15e9 clock cycles to complete the program. The CPU clock cycle
time is 500e-12 second, i.e., 500 picoseconds.
How many seconds is the CPU performance for the task? - Answer-7.5
A cache has 16 one-word blocks. Memory blocks are mapped to fully associative
caches. Memory block is 15.
What is the cache position given the cache configuration and memory block? - Answer-
Any of the 16 cache blocks
A program has a CPI of 10 on a target platform. The processor pipeline is expanded
and clock rate is increased by a factor of 5, but the CPI fails to decrease accordingly.
Which factor is negatively affecting performance? - Answer-Cache memory
Four processors (1, 2, 3, and 4) have clock frequencies of 200 Mhz, 300 Mhz, 500 Mhz,
and 700 Mhz, respectively.
Suppose:
Processor 1 can execute an instruction with an average of 5 steps.
Processor 2 can execute an instruction with an average of 3 steps.
Processor 3 can execute an instruction with an average of 3 steps.
Processor 4 can execute an instruction with an average of 5 steps.
, Which processor should be selected to improve performance for the execution of the
same instruction? - Answer-Processor 3
Which technique should be implemented to reduce cache miss rate? - Answer-Blocking
Which set-associative cache will improve overall performance? - Answer-Two-way
A program requires one billion instructions to execute on a processor running at 4 GHz.
Exactly 50% of the instructions execute in three clock cycles, 30% execute in four clock
cycles, and 20% execute in five clock cycles resulting in an execution time of 1.075
seconds.
Which adjustment improves overall performance by 12%? - Answer-70% execute at
three cycles and 30% at four cycles
Which instruction of the ARM architecture excludes a carry value after the arithmetic
calculation? - Answer-Reverse subtract
Which three components or aspects specify the statement of a virtual machine? -
Answer-Page table
Program counter
Registers
A storage solution for video editing is being planned. The requirements are:
Largest storage space
No redundancy
Fastest I/O speed
Which RAID solution should be implemented? - Answer-RAID 0
Which computer architecture idea is analogous to the assembly line? - Answer-
Performance via pipelining
What is an advantage of using virtual memory technique? - Answer-It permits a program
to exceed the size of primary memory.
What is an advantage of implementing cloud computing? - Answer-It provides automatic
scaling.
Which performance benefit do 128-bit wide registers in SSE2 streaming SIMD
extensions enable? - Answer-Parallel arithmetic computations
What is the bit width of an SIMD register with the suffix of 'D' when determining subword
parallelism? - Answer-64-bit
Which register holds the result for the instruction
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