Exam (elaborations)
CS 250 Midterm 2 Correct Answers Latest Update
- Course
- CS 250
- Institution
- Rutgers University
CS 250 Midterm 2 Correct Answers Latest Update
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Solution 2024/2025Pepper
CS 250 Correct Answers Latest Update
IEEE float ANS✔✔ +/- 1.YYYYYY * 2^(exp - 127)
1 bit sign, 8-bit exp, 23-bit mantissa (Y)
memory layout ANS✔✔ stack - local
heap - dynamic (new/malloc)
data - global
text - instructions
note - if you malloc, the pointer is on the stack; the thing it points to is in
the heap
ISA ANS✔✔ instruction set architecture
"contract between hardware and software"
specifies WHAT - what instructions? how many registers?
microarchitecture ANS✔✔ how you implement ISA in hardware
Von Neumann ANS✔✔ fetch -> decode -> read -> execute -> write -> next
program counter ANS✔✔ memory address of current instruction
register ANS✔✔ data storage on processor for fast operations
, Solution 2024/2025
Pepper
MIPS format ANS✔✔ 6-bit opcode, 26-bit operand
I-type, J-type, R-type
rd, rs, rt except for sw
stack pointers ANS✔✔ used to specify stack frame of a procedure call -->
every time you JAL (before calling and/or when called)
addi $sp, $sp, -(# of things saved * 4)
sw $reg, x($sp)
DO THINGS
lw $reg, x($sp)
addi $sp, $sp, +(# of things * 4)
basically mirror image
RISC ANS✔✔ reduced instruction set architecture
simplified (limited?) set of instructions to make implementation & compiling
easier
MIPS is a RISC
some logic stuff:
MUX
decoder
tri-state
register file ANS✔✔ MUX - 2^x inputs + x-bit selector --> output 1 thing
decoder - x-bit input, 2^x outputs, only xth is 1
tri-state - output 0, 1, or Z (no-effect) --> use with a decoder
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