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2019 Hardware Design Past paper
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Hardware Design Past papers for 2018 and 2019. They contain hand written answers that include VHDL codes and some screenshots to better understand the answer.
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King’s College LondonThis paper is part of an examination of the College counting towards the
award of a degree. Examinations are governed by the College Regulations
under the authority of the Academic Board.
Degree Programmes BEng, MEng
Module Code 6CCS3HAD
Module Title Hardware Design
Examination Period May 2019 (Period 2)
Time Allowed 3 hours
Rubric FOUR questions in total
ONE question from Section A
THREE questions from Section B
ANSWER EACH QUESTION ON A NEW PAGE OF YOU ANSWER BOOK AND
WRITE ITS NUMBER IN THE SPACE PROVIDED
Notes Books, notes or other written material may not be
brought into this examination
Calculators Calculators may be used. The following models are
permitted:
Casio fx83
Casio fx85
A VHDL DATASHEET HAS BEEN INCLUDED AT THE END OF THIS
PAPER
PLEASE DO NOT REMOVE THIS PAPER FROM THE EXAMINATION ROOM
,S E C T I O N: A
Answer either Question 1 or Question 2 but not both
1. Question one
(a) What are the three different styles of modelling in VHDL and in
what situations would you use each of them?
[4 marks]
(b) The following VHDL entity describes the interfaces for a 6-input
XOR gate. Give three alternative architectures which will perform
the required function of the entity XOR6 using each of the styles
you described in the answer to (a).
entity XOR6 is
port( A: in std_logic_vector(5 downto 0);
B: out std_logic);
end entity XOR6;
[15 marks]
(c) When and why are components used in VHDL? Describe the
three steps required in using components in VHDL ’87. Support your
answer by using the analogy of integrated circuits on a printed
circuit board.
[6 marks]
See Next Page
, 1) ④ Distant styles of modelling ;
Behavioural is used to describe complex circuits .
•
-
→ which
architecture block
in
the
is done in
model
defined inside to
•
are
processes
sequential circuits .
the sizable
• not
all
syn
connecting instantiated components
to
- Structural → •
circuit
define functionality of a
.
level )
easily synthesiszab.ie (gate
-
•
-
Dataflow → •
output data as a function of
input .
used describe com_bi at circuits
.
• to
RHS exp;
concurrent assignment LHS -
⇐
•
↳ value is assigned to a
signal .
③
YE1H
6 -
;i:÷
26=64 combinations o
behavioural → process (A)
i -7¥
-
-
structural → component ; ÉE¥
" ←
s
:;É T
- Dataflow A0
As
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