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Question Bank-System Verilog
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Contains model Questions and programs for system verilog concepts
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Q:Create a structure called "st_fruit"// which to store the fruit's name, count and expiry date in days.
// Note: this structure declaration can also be placed outside the module
module tb;
// Create a structure called "st_fruit"
// which to store the fruit's name, count and expiry date in
days.
// Note: this structure declaration can also be placed
outside the module
struct {
string fruit;
int count;
byte expiry;
} st_fruit;
initial begin
// st_fruit is a structure variable, so let's initialize it
st_fruit = '{"apple", 4, 15};
// Display the structure variable
$display ("st_fruit = %p", st_fruit);
// Change fruit to pineapple, and expiry to 7
st_fruit.fruit = "pineapple";
st_fruit.expiry = 7;
$display ("st_fruit = %p", st_fruit);
end
endmodule
Q Write an assertion check to make sure that a signal is high for a minimum
of 1 cycles and a maximum of 5 cycles.
property a_min_1_max_5: @(posedge clk)
$rose(a) |-> a[*1:5] ##1 (a==0)
, endproperty
assert property (a_min_1_max_5);
///
Signal “a” is asserted high on each clock cycle
b) If “a” is high in a cycle after two clock cycles, signal “b” has to be asserted
high.
For a synchronous FIFO of depth=64, write an assertion for following
scenarios. Assume a clock signal (clk), write and read enable signals, full flag
and a word counter signal.
1) If the word count is >63, FIFO full flag is set.
2) If the word count is 63 and a new write operation happens without a
simultaneous read, then the FIFO full flag gets set.
Answer :
assert property (@(posedge clk) disable iff (rst) (wordcnt>63 |-> fifo_full));
assert property (@(posedge clk) disable iff (rst) (wordcnt==63 && write_en &&
!read_en |=> fifo_full));
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