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Summary 1.1 - systems architecture

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GCSE OCR COMPUTER SCIENCE J277 1.1 - SYSTEMS ARCHITECTURE 1.1.1 Architecture of the CPU, 1.1.2 CPU performance, 1.1.3 Embedded systems

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  • August 26, 2022
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  • 2021/2022
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The CPU is the Central Processing Unit. It is used to execute instructions stored in memory using the
fetch-decode-execute cycle. The CPU contains the ALU, CU, the cache and several registers.

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The Control Unit (CU)
Ao.odo, - -> manages the fetch-decode-execute cycle
Ac.oAos ct vv1
P.o 1' ) controls the flow of data inside the CpU and outside the CpU
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The Arithmetic and Logic Unit (AtU)
; carries out arithmetic calculations such as addition/subtraction Co*,? a.StOr,S S\lr CU\ ctS
) carries out logical calculations such as AND/OR/NOT
) contains the accumulator

The cache
) fast memory in the CPU. slower than registers but faster than RAM
) stores regularly used data
) Iow capacity, expensive compared to RAM

The fetch-decode-execute cycle
) memory address is copied from the program counter to MAR
, the instruction in the MAR address is copied to the MDR {el-c[.
) increment the program counter
; instruction in MDR is decoded by control unit
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Ju.o r(q o) o.+Sio(e |Lta ccannpvtaerrtt witt^i.,,
) the instruction if executed tLc cPU [t^q[^eeob k ac\-
h ho\Ainfonvlahanr un""doJ for tt-r C?U lowa/c,t^olAs ( Woi(ic 1ie.n o{ ,*[*,.,tatou
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The Von Neumann architecture describes a system where the CPU runs programs stored in memory.
Registers temporarily hold bits of data needed by the CpU
) Proglam Counter (PC) - holds the memory address of the next instruction to be processed
; Accumulator (ACC) - results of operations carried out by the ALU are stored
; MemoryAddress Register (MAR) - holds the memory location of the current instruction to be fetched
-)Memory Data Register (MDR) - holds data when it is fetched from memory or data that is waiting to be
written to memory


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