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ENGR 325 HOMEWORK #3 45 7 8 9 2........

xam (elaborations) ENGR 325 HOMEWORK #3 KEY Exam (elaborations) ENGR 325 HOMEWORK #4 KEY Exam (elaborations) ENGR 325 HOMEWORK #5 KEY Exam (elaborations) ENGR 325 HOMEWORK #9 KEY Exam (elaborations) ENGR 325 HOMEWORK #2 KEY Exam (elaborations) ENGR 325 HOMEWORK #1 ANSWER KEY Exam (elabo...

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ENGR 325 HOMEWORK 7.

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(5) In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. Assume each word is a 32-bit integer. (P&H 5.1, §5.1) for (I=0; I<8; I++) for (J=0; J<8000; J++) A[I][J]=B[I][...

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ENGR 325 HOMEWORK #8 ANSWER KEY

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5) Recall that we have two write policies and write allocation policies, and their combination can be implemented either in L1 or L2 cache. Assume the following choice for L1 and L2 caches: L1 L2 Write-through, non-write allocate Write-back, write allocate Describe the procedure of handling an L...

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ENGR 325 HOMEWORK #1 ANSWER KEY

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(5) Aside from the smart cell phones used by a billion people, list and describe four other types of computers. (P&H 1.1, §1.1) SOLUTION:  Desktop PC – relatively powerful, single user, personal machine  Server – more powerful, large workloads or many small tasks, reliable  Superc...

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ENGR 325 HOMEWORK #2 KEY

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. (5) For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, and h are given and could be considered 32-bit integers as declared in a C program. Use a minimal number of MIPS instructions. (P&H 2.1, §2.2) f = g + (h – 5); SOLUTION: Since f...

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ENGR 325 HOMEWORK #5 KEY

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(5) Assume that the logic blocks needed to implement a processor’s datapath have the latencies shown in the table below. These problems refer to the datapath element Shift-Left-2. (P&H 4.4, §4.3) Block Latency (ps) I-Mem 200 Add 70 Mux 20 ALU 90 Regs 90 D-Mem 250 Sign-Extend 15 Shift-L...

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ENGR 325 HOMEWORK #4 KEY

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1. (5) Consider the following instruction (P&H 4.1, §4.1): Instruction: AND Rd, Rs, Rt Interpretation: Reg[Rd] = Reg[Rs] AND Reg[Rt] a. What are the values of the control signals generated by the control in Figure 4.2 in the text for the above instruction? b. Which resources (blocks) perform a...

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ENGR 325 HOMEWORK #3 KEY

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(5) What is 5ED4 – 07A4 when these values represent unsigned 16-bit hexadecimal numbers? The result should be written in hexadecimal. Show your work. (P&H 3.1, §3.2) SOLUTION: 5ED4 - 07A4 0x5730 2. (5) What is 5ED4 – 07A4 when these values represent signed 16-bit hexadecimal numbers stor...

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