CPS 310 Midterm Review || with 100% Error-free Answers.
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Course
CPS 310
Institution
CPS 310
Instruction Set Architecture
(ISA) correct answers view of a machine which
corresponds to the machine and assembly language levels
compiler correct answers translates a high level language, which is architecture
independent, into assembly language, which is architecture dependent
assembler...
CPS 310 Midterm Review || with 100% Error-free Answers.
Instruction Set Architecture
(ISA) correct answers view of a machine which
corresponds to the machine and assembly language levels
compiler correct answers translates a high level language, which is architecture
independent, into assembly language, which is architecture dependent
assembler correct answers translates assembly language programs into executable
binary code
• For fully compiled languages like C and Fortran, the binary codes are
executed directly by the target machine. Java stops the translation at the
byte code leve correct answers
A compiled program is ...
how cpu executes it correct answers 1. copied from hard disk to memory
2. reads instructions and data from memory , executes results than stores back into memory
A word has how many bits? correct answers 32
In a byte addressable machine, the ____________ data that can be referenced in memory is the
_____________ correct answers smallest
byte
__________ is stored in a single memory location correct answers single byte data
____________- is stored as a sequence of bytes in a
number of memory locations correct answers
how to access single byte data and how to store and read correct answers 1. address of the
memory location holding single byte data holding
2. only one way to store/read data
how to access multi byte data and how to store and read correct answers 1. address of the
memory location is the same as the adress of the lowest byte
2. two ways big and little endian
Big Endian correct answers most significant byte has lowest address (stored first)
Little Endian correct answers least significant byte has lowest address (stored first)
SPARC stands for ___________________ correct answers scaleable processer achitechture
RISC (Subset of sparc) correct answers Reduced Instruction Set Computer
, The ARC ISA is a subset of the ________________ correct answers SPARC ISA
memory map 0 - 2048 is reserved for .....
user space is from..........
bottom of system stack is
what space is reserved for I/O devices correct answers OS
2048 to system stack
(2^31) - 4 and grows towards lower addresses
between 2^31 and (2^32)-1 (TREATED LIKE MEMORY DEVICES)
2^n bit address space ( n is how many bits) correct answers
hard allignment correct answers half words must have even addresses
words must have addresses that are multiples of 4
soft allignment correct answers unaligned memeory objects are permitted bt it may take longer
may requite more time (intel x86)
The CPU consists of which two parts? correct answers data section/datapath (registers and ALU)
and control section
arc is big endien correct answers
what are the two registers that that form interface between control unit and datapath correct
answers PC - program counter (OR INSTRUCTION POINTER FOR INTEL) and instruction
register IR
pointed by PC than stored and interpreted in IR
4 steps when exciting a program by control unit (fetch execute cycle) correct answers 1. fetch
next instruction from memory
2. decode opcode
3. read opcode from main memory if any
4. execute and store results if any
5. back to step 1
register file correct answers small fast memory, similar to main but not main, few to a few
thousand REGISTERS
instruction set differs for every processer.
expetion correct answers The set of instructions that the processor can execute.
diff processors have diff instructions which usually differ in size , type of operations and
operends , and complexity of instructions
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