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CPEN EXAM 2 STUDY GUIDE
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CPEN EXAM 2 STUDY GUIDE
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CPEN EXAM 2 STUDY GUIDEConcurrency - Answers -The capability of doing more than one operation at the same
time
Pipelining - Answers -A method of concurrency, a task is divided into subtasks, and
then overlap performance of the subtasks for multiple iterations of the task
Speedup factor - Answers -A calculation of how much pipelining will improve the speed
of an operation
Delayed loads - Answers -Can cause problems if the instruction immediately after the
load uses the value being loaded as an operand, needs to stall the pipeline
Data dependencies - Answers -One instruction needs to use data that are being
generated/manipulated by another instruction that might be in the pipeline at the same
time.
RAW - Answers -read after write
Data forwarding - Answers -the process of receiving data on one digital data link and
outputting the data onto another digital data link in the proper format.
WAR - Answers -write after read
WAW - Answers -Write after write
Out-of-order execution - Answers -A situation in pipelined execution when an instruction
blocked from executing does not cause the following instructions to wait.
Functional unit - Answers -Different parts of the ALU that instructions can be assigned
instructions by type.
Scoreboard method - Answers -Scheduling instruction execution was developed for the
CDC 6600 (released in 1964) by lead engineers James Thornton and Seymour Cray
Tomasulo's method - Answers -Developed for the IBM System/360 Model 91 (released
in 1967) by Robert Tomasulo for scheduling instruction execution
Register renaming - Answers -The use of dynamically generated tags to identify
operands, rather than the static CPU register numbers generated by the programmer
Superpipelining - Answers -The use of a very deep, high-speed pipeline for instruction
processing in a microprocessor
, Superscalar - Answers -Processors that can execute more than one instruction per
clock cycle
Instruction-level parallelism - Answers -Multiple instructions that are not dependent on
one another, and thus can be executed simultaneously if parallel hardware is available
Speculative execution - Answers -The ability of some CPU's to execute instructions
ahead of the current location and beyond a conditional branch.
The results of these instructions will be usable only if the CPU guessed the branch
direction correctly
Very Long Instruction Word (VLIW) - Answers -A style of instruction set architecture that
launches many operations that are defined to be independent in a single wide
instruction, typically with many separate opcode fields
Multithreading - Answers -Allows different parts of a single program to run concurrently
Arithmetic\logic unit - Answers -A component of a CPU that performs computations on
binary data
Registers - Answers -A component of a CPU that holds operands and memory
addresses for operands
Control unit - Answers -A component of a CPU that controls and sequences the
behavior of the other components
Fetch, Decode, Execute, Write Back - Answers -What are the steps of a simplified Von
Neumann cycle
Instruction Set Architecture (ISA) - Answers -The part of the computer architecture
related to programming, including the native data types, instructions, registers,
addressing modes, memory architecture, interrupt and exception handling, and external
I/O
bit fields - Answers -Subsets of bits that make up a machine language instruction format
Operation code - Answers -Leftmost bit field that determines the function of the overall
instruction. Using more for the bit field will mean the machine can handle more separate
instructions.
Register Selection - Answers -The second and forth bit fields. Determines which CPU
registers will be used by the instruction.
Equation for determining the amount of registers a machine has based on the register
selection - Answers -2^x
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